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ADE7566/ADE7569
Table 3. I 2 C-Compatible Interface Timing Parameters (400 kHz)
Preliminary Technical Data
Parameter
t L
t H
t SHD
t DSU
t DHD
t RSU
t PSU
t R
t F
t SUP 1
Description
SCLK low pulse width
SCLK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Rise time of both SCLK and SDATA
Fall time of both SCLK and SDATA
Pulse width of spike suppressed
Typ
1.36
1.14
251.35
740
400
12.5
400
200
300
50
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
1
Input filtering on both the SCLK and SDATA inputs suppresses noise spikes less than 50 ns.
t BUF
t SUP
t R
SDATA (I/O)
t PSU
t DSU
t SHD
MSB
t DHD
LSB
t H
t DSU
ACK
t RSU
t DHD
MSB
t F
t R
SCLK (I)
PS
1
2–7
t L
8
t SUP
9
S(R)
t F
1
STOP START
CONDITION CONDITION
Figure 3. I 2 C-Compatible Interface Timing
Rev. PrA | Page 10 of 136
REPEATED
START
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